InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Area of Science:

• Semiconductor Physics
• Materials Science
• Nanotechnology

Background:

• Hetero-structure tunnel junctions in gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) improve ON-state current.
• Existing GAA NW TFETs face limitations in drive current and scalability.

Purpose of the Study:

• To introduce a novel nanotube TFET concept utilizing a hetero-structure configuration.
• To demonstrate the potential for significantly higher drive current compared to GAA NW TFETs.
• To explore the benefits of core-shell gates for enhanced tunneling and reduced device footprint.

Main Methods:

• Numerical simulations were employed to analyze the performance of the proposed nanotube TFET.
• The study compared the proposed device against GAA NW TFETs of similar dimensions.

Main Results:

• The nanotube TFET design leverages a larger physical tunneling area through inner/outer core-shell gates.
• A 10 nm thin nanotube TFET with a 100 nm core gate demonstrated a 5x normalized output current compared to a 10 nm diameter GAA NW TFET.
• The nanotube configuration eliminates the need for arraying, saving real estate.

Conclusions:

• The hetero-structured nanotube TFET represents a significant advancement over GAA NW TFETs.
• This design offers a pathway to achieving higher drive currents and more compact electronic devices.
• The unique architecture provides enhanced performance and efficiency for future semiconductor applications.