Size and shape effect of SiC source/drain on strained Si

Area of Science:

• Materials Science
• Semiconductor Physics
• Device Engineering

Background:

• Strained silicon (Si) enhances carrier mobility in Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices.
• Epitaxially grown silicon carbide (SiC) source/drain regions induce channel strain due to lattice mismatch with the silicon substrate.
• Device layout parameters critically influence stress distribution and channel strain.

Purpose of the Study:

• To investigate the effect of device layout parameters on channel strain in MOSFETs.
• To quantify the impact of gate length, source/drain width, and elevation height on lateral channel strain.
• To provide insights for optimizing device design for improved carrier mobility.

Main Methods:

• Utilized the Finite Element Method (FEM) for accurate strain calculation.
• Employed a 3-dimensional model incorporating anisotropic material properties (elastic constant, Poisson's ratio).
• Simulated Si0.983C0.017 source/drain on a Si substrate with varying gate lengths (30-90 nm), source/drain widths (30-90 nm), and elevation heights (0-30 nm).

Main Results:

• Channel strain decreases with increasing gate length.
• Channel strain increases with increasing source/drain width.
• Shorter gate lengths and source/drain widths resulted in lower average channel strain for specific parameter combinations.
• The influence of source/drain elevation height on strain is interdependent with gate length and source/drain width.

Conclusions:

• Device layout parameters, specifically gate length and source/drain width, are critical determinants of channel strain.
• Optimizing these geometric factors is essential for maximizing the benefits of strained silicon in MOSFETs.
• The interplay between elevation height and other layout parameters necessitates careful design considerations.