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Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

Equivalent Capacitance

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Multiple capacitors can be connected in a circuit in series or parallel configuration. When the capacitor combination is connected to a battery, the potential drop across each capacitor and the magnitude of charge stored in the individual capacitor depends on the type of the connection. The capacitor combination is replaced by a single equivalent capacitor that stores the same amount of charge as the combination for a given potential difference.
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Equivalent Capacitance

Equivalent Capacitance

From the study of resistive circuits, it is understood that employing a series-parallel combination serves as an effective strategy for simplifying circuits. Capacitors can be arranged within a circuit in one of two ways: a series configuration or a parallel configuration. The way these capacitors are connected to a battery will influence both the potential drop across each individual capacitor and the size of the charge that each capacitor can store. This is determined by the specific type of...

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MOS Capacitor

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Related Experiment Video

Updated: Apr 11, 2026

Scanning-probe Single-electron Capacitance Spectroscopy

Scanning-probe Single-electron Capacitance Spectroscopy

Published on: July 30, 2013

Performance analysis of a digital capacitance measuring circuit.

Lijun Xu¹, Shijie Sun¹, Zhang Cao¹

¹Key Laboratory of Ministry of Education for Precision Opto-Mechatronics Technology, School of Instrument Science and Opto-Electronic Engineering, Beihang University, Beijing 100191, China.

The Review of Scientific Instruments

|June 1, 2015

Summary

This summary is machine-generated.

This study details a digital capacitance measuring circuit, evaluating its performance through simulation and experiments. The circuit demonstrates reliable capacitance measurement, with potential for improved signal-to-noise ratio (SNR) and standard deviation using advanced data processing.

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Area of Science:

Electrical Engineering
Measurement Science

Background:

Accurate capacitance measurement is crucial for various electronic applications.
Existing methods may face limitations in precision and dynamic range.
Digital circuits offer potential for enhanced measurement capabilities.

Purpose of the Study:

To design and analyze a digital capacitance measuring circuit.
To evaluate its static and dynamic performance metrics.
To validate simulation findings with experimental results.

Main Methods:

Theoretical analysis of circuit design.
Numerical simulation to assess signal-to-noise ratio (SNR) and standard deviation.
Experimental evaluation of circuit performance across a range of capacitances.

Main Results:

Simulation showed SNR decreasing from 90 dB to 22 dB for capacitance from 6 pF to 3 fF.
Experiments yielded SNR from 88 dB to 40 dB for capacitance from 6 pF to 40 fF.
Standard deviation ranged from 0.17 fF to 0.25 fF; maximum errors were 5.12 fF and 1.26%.

Conclusions:

The digital capacitance measuring circuit exhibits robust performance.
Further improvements in SNR and standard deviation are achievable by averaging data over multiple periods.
The circuit is suitable for precise capacitance measurements.