Ring Counter Based ATPG for Low Transition Test Pattern Generation.

Area of Science:

• Electrical Engineering
• Computer Engineering
• VLSI Design

Background:

• Dynamic power dissipation increases during random test pattern application in integrated circuits.
• High switching transitions between test patterns lead to increased power consumption during testing.

Purpose of the Study:

• To propose a novel ring counter-based automatic test pattern generator (RC-ATPG) for reducing dynamic power dissipation.
• To enhance test pattern correlation and minimize switching transitions during integrated circuit testing.

Main Methods:

• Developed an RC-ATPG incorporating an external circuit with XOR gates, full adders, and multiplexers.
• Implemented test vector insertion between less correlative test patterns to increase pattern correlation.
• Determined total transitions and inserted vectors to reduce dynamic power dissipation.

Main Results:

• The proposed RC-ATPG significantly reduces vertical switching transitions compared to conventional ATPG methods.
• Achieved an average power reduction of 38.5% and peak power reduction of 50% in ISCAS'85 and ISCAS'89 benchmark circuits.
• Demonstrated reduced dynamic power dissipation with a small decoding logic size.

Conclusions:

• The RC-ATPG effectively reduces dynamic power dissipation during testing by minimizing switching transitions.
• Test vector insertion strategy enhances test pattern correlation, leading to improved power efficiency.
• The method offers a practical approach for power-aware testing in VLSI circuits.