Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Area of Science:

• Analog circuit design
• Neural network hardware
• VLSI systems

Background:

• Traditional Euclidean (L2) distance calculations can be computationally intensive.
• Manhattan (L1) distance offers a less complex alternative with reduced power and hardware requirements.
• Analog circuits are suitable for efficient, parallel processing in neural networks.

Purpose of the Study:

• To present a programmable analog current-mode circuit for calculating vector distances.
• To enable switching between L1 and L2 distance measures.
• To integrate this circuit into an analog winner-take-all neural network.

Main Methods:

• Design and implementation of a current-mode distance calculation circuit (DCC).
• Fabrication of the DCC using 0.18-µm CMOS technology.
• Integration of the DCC into an analog winner-take-all neural network and laboratory testing.

Main Results:

• The programmable DCC successfully calculates both L1 and L2 distances.
• The circuit operates efficiently with lower power consumption (55 µW) and higher data rates (12 MHz) in L1 mode compared to L2 mode (85 µW, 10 MHz).
• The fabricated neural network demonstrated successful learning processes verified by lab tests.

Conclusions:

• The proposed DCC is a simple, hardware-efficient component for analog neural networks.
• Programmability for L1 and L2 distances enhances flexibility and performance.
• The circuit's small area (3900 µm²) makes it suitable for large-scale parallel neural network implementations.