Balancing the Lifetime and Storage Overhead on Error Correction for Phase Change Memory.

Area of Science:

• Computer Engineering
• Materials Science
• Semiconductor Memory

Background:

• DRAM scaling faces energy and reliability challenges, prompting research into nonvolatile memory alternatives.
• Phase Change Memory (PCM) is a promising nonvolatile memory technology for main memory applications.
• Reliability is crucial for PCM adoption, with wear-out errors well-studied, but transient errors receiving less attention.

Purpose of the Study:

• To propose an innovative mechanism, Local-ECC-Global-ECPs (LEGE), to address both soft and hard errors in PCM memory systems.
• To enhance the reliability and stability of PCM-based computer systems.
• To reduce the storage overhead and access latency associated with error correction in PCM.

Main Methods:

• Deployment of a local error correction code (ECC) for each data line to detect and correct one-bit errors.
• Implementation of a global error correction pointers (ECPs) buffer for the entire memory chip to correct hard error bits.
• Comparison of the LEGE mechanism with existing solutions like ECP-6 and PAYG.

Main Results:

• The LEGE mechanism provides comparable lifetimes to ECP-6 while reducing storage overhead by approximately 50%.
• LEGE reduces access latency overhead by approximately 3.55% compared to the PAYG solution.
• LEGE achieves this performance improvement with only a 1.61% increase in storage overhead compared to PAYG.

Conclusions:

• The LEGE mechanism offers a robust solution for mitigating both transient and wear-out errors in PCM memory.
• LEGE significantly improves storage efficiency and reduces access latency, making PCM a more viable main memory technology.
• This approach enhances the overall reliability and performance of next-generation nonvolatile memory systems.