A FPGA Implementation of JPEG Baseline Encoder for Wearable Devices

Area of Science:

• Digital Signal Processing
• Embedded Systems Engineering
• Computer Vision

Background:

• Wearable devices require efficient image compression for health and wellness applications.
• Field-Programmable Gate Arrays (FPGAs) offer a flexible hardware solution for real-time processing.
• Balancing performance and resource utilization is critical for embedded systems.

Purpose of the Study:

• To present an efficient FPGA implementation of the JPEG baseline encoder for wearable health and wellness devices.
• To leverage High-Level Synthesis (HLS) for flexible FPGA software development and optimized resource utilization.
• To validate the performance of the proposed FPGA implementation in a real-world system.

Main Methods:

• Utilized High-Level Synthesis (HLS) tool for system design and FPGA implementation.
• Developed an optimized dataflow configuration with a padding scheme for simplified data transfer timing control.
• Integrated and tested the JPEG encoder on a system-on-chip (SoC) multi-sensor platform.

Main Results:

• Achieved efficient real-time performance for JPEG baseline image compression.
• Demonstrated effective balance between computational efficiency and FPGA resource utilization.
• Verified the implementation's suitability for wearable health and wellness applications through experimental validation.

Conclusions:

• The proposed FPGA implementation of the JPEG baseline encoder is efficient and suitable for wearable devices.
• HLS provides flexibility and aids in optimizing performance and resource usage for embedded image compression.
• The validated design meets the demands of real-time processing in health and wellness applications.