A New Arbiter PUF for Enhancing Unpredictability on FPGA.

Area of Science:

• Computer Engineering
• Cybersecurity
• Hardware Security

Background:

• Conventional Arbiter-based Physically Unclonable Functions (PUFs) exhibit limited response unpredictability.
• The N-XOR Arbiter PUF is a known method to enhance unpredictability but has limitations.
• Field-programmable gate arrays (FPGAs) require robust security primitives like PUFs.

Purpose of the Study:

• To introduce and evaluate a novel Double Arbiter PUF design for enhanced unpredictability on FPGAs.
• To compare the proposed Double Arbiter PUF against conventional N-XOR Arbiter PUFs.
• To analyze the machine-learning attack tolerance and intrachip variation of the Double Arbiter PUF.

Main Methods:

• Implementation of a novel Double Arbiter PUF architecture on FPGAs.
• Comparative analysis with N-XOR Arbiter PUFs using machine-learning attack simulations.
• Evaluation of uniqueness, randomness, and steadiness metrics for both PUF designs.
• Assessment of intrachip variation to understand attack tolerance.

Main Results:

• The Double Arbiter PUF demonstrates significantly higher unpredictability and tolerance to machine-learning attacks.
• Reduced dependency on the number of training samples for machine learning attacks was observed for the Double Arbiter PUF.
• Intrachip variation analysis explains the enhanced robustness of the Double Arbiter PUF.
• The 3-1 Double Arbiter PUF configuration achieved the best overall performance across all evaluated metrics.

Conclusions:

• The Double Arbiter PUF is a superior alternative to conventional Arbiter PUFs for enhancing hardware security on FPGAs.
• The proposed design offers improved resilience against sophisticated machine-learning-based attacks.
• The 3-1 Double Arbiter PUF is recommended for applications demanding high unpredictability and robustness.