FPGA Implementation of Optimal 3D-Integer DCT Structure for Video Compression.

Area of Science:

• Digital Signal Processing
• Hardware Implementation
• Image and Video Compression

Background:

• Discrete Cosine Transform (DCT) is crucial for image and video compression.
• Efficient hardware implementation of 3D-DCT is challenging, especially with integer approximations.
• Field-Programmable Gate Arrays (FPGAs) offer a flexible platform for such implementations.

Purpose of the Study:

• To propose a novel optimal structure for 3D-integer Discrete Cosine Transform (DCT).
• To identify an integer set that balances Mean Squared Error (MSE), coding efficiency, and hardware complexity for FPGA implementation.
• To minimize resource utilization and power dissipation in 3D-DCT hardware.

Main Methods:

• Analysis of various integer approximation methods for 3D-DCT.
• Evaluation of integer sets based on MSE, coding efficiency, power dissipation, and hardware complexity.
• Implementation and performance comparison on FPGAs using different integer sets.

Main Results:

• Shorter bit-value integer sets generally utilize fewer hardware resources.
• The direct computation method using the integer set [10, 9, 6, 2, 3, 1, 1] demonstrated superior performance.
• This specific integer set achieved better resource utilization and lower power dissipation compared to alternatives.

Conclusions:

• The proposed 3D-integer DCT structure optimizes hardware implementation on FPGAs.
• The integer set [10, 9, 6, 2, 3, 1, 1] is identified as optimal for achieving high coding efficiency and low resource usage.
• This research contributes to more efficient video compression hardware designs.