Fast underdetermined BSS architecture design methodology for real time applications.

Area of Science:

• Signal Processing
• Computer Architecture

Background:

• Under-determined Blind Source Separation (UBSS) is crucial for real-time applications where sensor count is less than source count.
• Existing UBSS algorithms face speed limitations, hindering real-time performance.

Purpose of the Study:

• To propose a high-speed architecture design methodology for UBSS.
• To leverage a novel high-speed Discrete Hilbert Transform (DHT) for enhanced UBSS performance.

Main Methods:

• Developed a high-speed DHT architecture using a sub-matrix multiplication method for M-point computation recursively from N-point architecture.
• Implemented the DHT architecture and a state-of-the-art architecture in VHDL for 16-bit word length.
• Performed ASIC implementation using UMC 90-nm technology at 1V and 1MHz clock frequency.

Main Results:

• The proposed DHT architecture achieves a computation speed that is two times faster than the state-of-the-art architecture.
• Experimental comparisons validate the significant speed improvement of the DHT-based UBSS design.

Conclusions:

• The proposed high-speed DHT architecture significantly accelerates UBSS algorithms.
• This methodology is well-suited for real-time signal processing applications requiring efficient source separation.