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A Vertically Integrated Junctionless Nanowire Transistor.

Byung-Hyun Lee1,2, Jae Hur1, Min-Ho Kang3

  • 1School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.

Nano Letters
|February 18, 2016
PubMed
Summary
This summary is machine-generated.

This study introduces the first vertically integrated junctionless field-effect transistor (VJ-FET) using stacked silicon nanowires. This novel device reduces variability and fabrication complexity compared to previous designs, improving performance for applications like nonvolatile memory.

Keywords:
Silicon nanowire (SiNW)gate-all-around (GAA)junctionless transistorone-route all-dry etchthree-dimensional nonvolatile memoryvertical integration

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Area of Science:

  • Semiconductor device physics
  • Nanotechnology
  • Materials science

Background:

  • Vertically integrated multi-nanowire field-effect transistors (VM-FETs) face challenges with variability and complex fabrication.
  • Existing inversion-mode FETs (IM-FETs) suffer from surface conduction variability.
  • Junction formation in vertically stacked devices is difficult and can damage the silicon nanowires (SiNWs).

Purpose of the Study:

  • To demonstrate the first vertically integrated junctionless field-effect transistor (VJ-FET) on a bulk silicon wafer.
  • To address the variability and fabrication complexity issues in VM-FETs.
  • To explore the potential of VJ-FETs in nonvolatile flash memory applications.

Main Methods:

  • Fabrication of a VJ-FET using vertically stacked silicon nanowires (SiNWs) with a gate-all-around (GAA) structure.
  • Utilizing the junctionless field-effect transistor (JL-FET) architecture for bulk conduction.
  • Comparative analysis with inversion-mode FETs (IM-FETs) and VM-FETs.

Main Results:

  • Successful demonstration of a VJ-FET on a bulk silicon wafer.
  • Alleviation of variability through bulk conduction in the SiNW core, unlike surface conduction in IM-FETs.
  • Reduced fabrication complexity due to the absence of source and drain (S/D) doping requirements.

Conclusions:

  • The VJ-FET architecture offers a promising solution to overcome limitations in vertically integrated nanowire devices.
  • Improved endurance and retention characteristics are observed when VJ-FETs are utilized as nonvolatile flash memory.
  • The junctionless approach simplifies fabrication and enhances device performance.