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Bayesian Estimation and Inference Using Stochastic Electronics.

Chetan Singh Thakur1, Saeed Afshar1, Runchun M Wang1

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Summary
This summary is machine-generated.

This study implements hardware for real-time Bayesian inference using stochastic circuits. Two systems, BEAST and BIND, demonstrate probabilistic algorithms for tracking and Directed Acyclic Graph inference, showcasing noise robustness.

Keywords:
Bayesian inferenceHidden Markov modelsSequential Monte Carlo samplingdirect acyclic graphneuromorphic engineeringprobabilistic graphical modelsspiking neural networksstochastic computation

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Area of Science:

  • Hardware implementation of probabilistic algorithms
  • Real-time Bayesian inference
  • Stochastic computing circuits

Background:

  • Bayesian inference problems are computationally intensive.
  • Emerging integrated circuit technologies face noise challenges.
  • Need for robust hardware solutions for probabilistic computations.

Purpose of the Study:

  • Demonstrate real-time Bayesian inference in hardware.
  • Implement probabilistic algorithms using a unified set of building blocks.
  • Showcase noise robustness of stochastic electronic implementations.

Main Methods:

  • Implemented Bayesian Estimation and Stochastic Tracker (BEAST) for Hidden Markov Model (HMM) based target tracking.
  • Developed Bayesian INference in DAG (BIND) using stochastic circuits for Directed Acyclic Graph (DAG) inference.
  • Utilized simple digital logic gates for building block implementation.

Main Results:

  • BEAST successfully tracked a target in real-time, learning transition and observation models, and external noise probabilities.
  • BIND demonstrated inference in DAGs using stochastic circuits.
  • Stochastic electronic implementation showed robustness to noise, crucial for nanometer-scale ICs.

Conclusions:

  • Hardware implementation of Bayesian inference is feasible using stochastic circuits.
  • The proposed building blocks enable real-time probabilistic computations.
  • Stochastic computing offers a noise-resilient approach for future integrated circuits.