Embedded Streaming Deep Neural Networks Accelerator With Applications.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Embedded Systems

Background:

• Deep convolutional neural networks (DCNNs) are crucial for visual perception tasks in various applications like autonomous systems and mobile devices.
• High throughput and power efficiency are critical for DCNN feedforward evaluation in real-world embedded platforms.
• Field-programmable gate array (FPGA)-based accelerators are increasingly proposed to meet these demands for DCNNs.

Purpose of the Study:

• To present an optimized streaming method for DCNN hardware accelerators on embedded platforms.
• To develop a compiler-like approach transforming high-level DCNN representations into executable operation codes.
• To maximize computational resource utilization through a novel scheduled routing topology.

Main Methods:

• An optimized streaming method was developed, functioning as a compiler for DCNN hardware acceleration.
• A novel scheduled routing topology was employed, integrating data reuse and concatenation.
• The method was implemented and tested on a Xilinx Kintex-7 XC7K325T FPGA accelerator, exploring weight-level and node-level parallelizations.

Main Results:

• The system achieved a peak performance of 247 G-ops.
• The hardware accelerator consumed less than 4 W of power.
• The system demonstrated high-performance efficiency in object classification and detection tasks, outperforming existing platforms.

Conclusions:

• The proposed optimized streaming method offers an efficient solution for DCNN hardware acceleration on embedded platforms.
• The novel approach effectively balances high performance with low power consumption.
• This work contributes to advancing DCNN applications in resource-constrained environments.