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Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film
Jae Hyo Park1,2, Gil Su Jang1,2, Hyung Yoon Kim1,2
1Department of Material Science and Engineering, Seoul National University, Seoul 151-742, Republic of Korea.
Scientific Reports
|April 22, 2016
Summary
Researchers achieved a record low subthreshold slope in low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) using novel gate dielectrics. This breakthrough enables ultra-low operating voltages for next-generation displays.
Area of Science:
- Materials Science
- Electrical Engineering
- Semiconductor Physics
Background:
- Achieving sub-kT/q subthreshold slope (SS) in low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) is crucial for advancing active-matrix organic-light emitting diode (AMOLED) displays.
- Current LTPS-TFT technology faces limitations in operating voltage and efficiency, hindering the development of next-generation displays.
Purpose of the Study:
- To demonstrate a sub-kT/q SS in LTPS-TFTs using a novel gate dielectric structure.
- To investigate the performance characteristics, including operating voltage and mobility, of these advanced LTPS-TFTs.
- To evaluate the reliability of LTPS-TFTs with negative capacitance under various stress conditions.
Main Methods:
- Fabrication of LTPS-TFTs utilizing a gate dielectric stack comprising polycrystalline-Pb(Zr,Ti)O3 (PZT) and ZrTiO4 (ZTO).
- Electrical characterization to measure subthreshold slope (SS), operating voltage, and carrier mobility.
- Reliability testing including DC negative bias stress, hot carrier stress, and self-heating stress analysis.
Main Results:
- Demonstrated a sub-kT/q SS of 31.44 mV/dec in LTPS-TFTs with PZT/ZTO gate dielectrics, a first for this configuration.
- Achieved an ultra-low operating voltage of -0.5 V in the weak inversion region.
- Reported the highest carrier mobility to date for LTPS-TFTs, reaching 250.5 cm²/Vsec.
- Investigated the reliability of these devices under various stress conditions, noting accelerated SS degradation under self-heating stress due to the PZT Curie temperature.
Conclusions:
- The integration of PZT/ZTO gate dielectrics enables unprecedented sub-kT/q SS and ultra-low operating voltages in LTPS-TFTs.
- These findings represent a significant advancement for the development of energy-efficient and high-performance AMOLED displays.
- Further research into mitigating self-heating effects is warranted to fully exploit the potential of these novel LTPS-TFTs.
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