Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

Area of Science:

• Digital circuit design
• Computer architecture
• VLSI design

Background:

• Asynchronous circuits offer potential advantages in speed and power efficiency over synchronous designs.
• Existing asynchronous full adder designs face challenges in optimizing both area and latency simultaneously.
• Early output logic in asynchronous adders can improve performance by reducing dependency on worst-case delays.

Purpose of the Study:

• To propose and evaluate two novel gate-level asynchronous full adder designs optimized for area and latency.
• To demonstrate the effectiveness of these designs within a 32-bit asynchronous ripple carry adder (RCA).
• To compare the performance of the proposed designs against existing asynchronous adder architectures.

Main Methods:

• Development of two early output asynchronous full adder designs using delay-insensitive dual-rail code and four-phase return-to-zero handshaking.
• Implementation of these full adders in a 32-bit asynchronous RCA.
• Performance evaluation in terms of latency, area, and cycle time using standard cells in a 32/28 nm CMOS process.

Main Results:

• One proposed full adder design achieved up to 67.8% reduction in latency and 32.6% reduction in area compared to other designs.
• Asynchronous RCAs utilizing the proposed full adders demonstrated significant reductions in cycle time, up to 97.5%.
• The designs achieved these improvements with negligible impact on power consumption.

Conclusions:

• The proposed early output asynchronous full adder designs offer a superior trade-off between area, latency, and cycle time.
• These designs are suitable for high-performance asynchronous digital systems.
• The findings contribute to the advancement of efficient asynchronous circuit design methodologies.