Simple Interface Engineering of Graphene Transistors with Hydrophobizing Stamps

Area of Science:

• Materials Science
• Nanotechnology
• Electronics Engineering

Background:

• Graphene transistors offer promising electronic properties but their performance can be limited by substrate interactions.
• Controlling the interface between graphene and the substrate is crucial for optimizing device characteristics.

Purpose of the Study:

• To develop a straightforward surface engineering method for fabricating improved graphene transistors.
• To investigate the impact of controlled substrate hydrophobicity on graphene transistor electrical properties.

Main Methods:

• Utilizing polydimethylsiloxane (PDMS) hydrophobizing stamps for contact-printing on silicon substrates.
• Engineering the silicon substrate surface to modify its contact angle.
• Fabricating and characterizing graphene transistors on both pristine and engineered substrates.

Main Results:

• Successful modification of silicon substrate contact angles via stamp printing.
• Demonstrated improvement in graphene transistor performance, including increased carrier mobility.
• Observed reduction in hysteresis in graphene transistors fabricated on engineered substrates.
• Proof-of-concept demonstration of a logic gate using both pristine and interface-engineered graphene devices.

Conclusions:

• The hydrophobizing stamp method provides a simple and effective route for surface engineering of silicon substrates.
• This technique significantly enhances the electrical characteristics and performance of graphene transistors.
• The developed method holds potential for advancing graphene-based electronic device fabrication and functionality.