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Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates
Liangliang Zhang1, Yuzheng Guo2, Vinayak Vishwanath Hassan3
1Department of Electrical Engineering, Stanford University , Stanford, California 94305, United States.
ACS Applied Materials & Interfaces
|June 28, 2016
Summary
Optimizing high-k/SiGe interfaces is crucial for electronics. Using aluminum gates selectively removes interfacial oxides, significantly reducing interface traps (Dit) for better device performance.
Area of Science:
- Materials Science
- Semiconductor Physics
- Surface Chemistry
Background:
- High-k dielectrics on SiGe substrates present interface challenges due to mixed Si/Ge oxides.
- Defective interfaces hinder SiGe's potential as a channel material in advanced electronic devices.
Purpose of the Study:
- To characterize the interfacial oxide structure of Al2O3/SiGe structures.
- To understand the impact of processing steps on interface quality.
- To identify methods for reducing interface trap densities (Dit).
Main Methods:
- Soft and hard X-ray photoelectron spectroscopy (XPS) were used to analyze surface layers.
- Atomic layer deposition (ALD) of Al2O3 and forming gas anneal with Pt gate metal were employed.
Main Results:
- As-received SiGe has native SiOx/GeOx layers, with GeOx beneath SiOx.
- Al2O3 ALD and annealing with Pt cause SiOx and GeOx regrowth, increasing Dit.
- Oxygen-scavenging Al gates selectively decompose interfacial oxides, leaving ultrathin SiOx and reducing Dit.
Conclusions:
- The native and regrown SiOx/GeOx layers create defective high-k/SiGe interfaces.
- Aluminum's oxygen-scavenging ability is key to forming a high-quality interface.
- Selective oxide decomposition by Al gates offers a pathway to drastically reduced interface trap densities.
