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A building block for hardware belief networks.

Behtash Behin-Aein1, Vinh Diep2, Supriyo Datta2

  • 1GLOBALFOUNDRIES Inc., Santa Clara, CA 95054, USA.

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|July 23, 2016
PubMed
Summary

This study introduces a novel transistor-like device for building probabilistic belief networks. This hardware approach offers a new foundation for probabilistic inference systems beyond traditional software methods.

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Area of Science:

  • Computer Science
  • Electrical Engineering
  • Artificial Intelligence

Background:

  • Probabilistic inference is crucial for complex problem-solving, often relying on software-based belief networks.
  • Current belief networks utilize standard transistors on deterministic hardware, limiting certain probabilistic computations.
  • There is a need for hardware-based solutions to enhance the capabilities of probabilistic networks.

Purpose of the Study:

  • To propose a novel transistor-like device as a fundamental building block for probabilistic networks.
  • To demonstrate the feasibility of implementing belief networks using this new hardware component.
  • To explore both reciprocal and non-reciprocal network structures with the proposed device.

Main Methods:

  • Development of a transistor-like device designed for probabilistic network applications.
  • Simulation of two proof-of-concept belief networks (reciprocal and non-reciprocal) using the proposed device.
  • Validation of device models through experimental benchmarking.

Main Results:

  • Successful simulation of reciprocal and non-reciprocal belief networks using the novel transistor-like device.
  • Demonstration of the device's potential as a hardware component for probabilistic inference.
  • Experimentally benchmarked models confirm the device's viability.

Conclusions:

  • The proposed transistor-like device offers a promising hardware alternative for constructing belief networks.
  • This approach could advance probabilistic inference by providing dedicated hardware components.
  • The study lays the groundwork for future development of hardware-accelerated probabilistic computing.