CU Partition Mode Decision for HEVC Hardwired Intra Encoder Using Convolution Neural Network.

Area of Science:

• Computer Engineering
• Digital Signal Processing
• Artificial Intelligence

Background:

• High Efficiency Video Coding (HEVC) intensive computation poses hardware overhead and power dissipation challenges for hardwired encoders.
• Software-based fast coding unit (CU) partition mode decision algorithms face efficiency degradation due to hardware design constraints.

Purpose of the Study:

• To develop a VLSI-friendly fast algorithm for HEVC encoding that reduces hardware complexity and power consumption.
• To maintain or improve the efficiency and parallelism of hardwired HEVC encoders.

Main Methods:

• A convolution neural network (CNN)-based fast algorithm was devised to reduce the number of CU partition modes processed per coding tree unit (CTU).
• The algorithm avoids dependencies on CU depth correlations or spatial proximity, preserving parallel processing capabilities.
• An accelerator was designed using TSMC 65-nm CMOS technology, leveraging optimal arithmetic representation for high-speed and low-cost implementation.

Main Results:

• An average of 61.1% intra-encoding time was saved with a Bjøntegaard-Delta bit-rate increase of 2.67%.
• The developed accelerator operates at 714 MHz (worst conditions), costs 42.5k gates, and consumes 16.2 mW at 714 MHz.
• A single accelerator supports HD1080p at 55 frames/s; four accelerators support UltraHD-4K at 55 frames/s.

Conclusions:

• The CNN-based fast algorithm effectively reduces HEVC encoder hardware complexity and encoding time while being suitable for parallel processing.
• The high-speed, low-cost accelerator demonstrates practical feasibility for real-time video encoding at various resolutions.
• The scalable architecture of the accelerator supports future demands for high-throughput video processing.