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Vertically Integrated Nanowire-Based Unified Memory.

Byung-Hyun Lee1,2, Dae-Chul Ahn1, Min-Ho Kang3

  • 1School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.

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|September 1, 2016
PubMed
Summary
This summary is machine-generated.

This study introduces a novel vertically integrated unified memory (VIUM) device combining dynamic random access memory (DRAM) and flash memory in one transistor. The five-story nanowire device demonstrates enhanced performance and endurance for advanced system-on-chip architectures.

Keywords:
1T-DRAMNAND flash memoryVertically integrated nanowireone-route all-dry etching processunified memoryzRAM

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Area of Science:

  • Semiconductor device physics
  • Nanotechnology
  • Materials science

Background:

  • Traditional memory architectures face limitations in integration density and performance.
  • Combining different memory types like DRAM and flash memory on a single chip is challenging.
  • Nanowire-based devices offer potential for novel memory integration.

Purpose of the Study:

  • To demonstrate a vertically integrated nanowire-based device for multifunctional unified memory.
  • To combine dynamic random access memory (DRAM) and flash memory functionalities within a single transistor.
  • To explore the potential of this unified memory for system-on-chip (SoC) applications.

Main Methods:

  • Fabrication of a vertically integrated unified memory (VIUM) device using a gate-all-around (GAA) structure on a bulk silicon wafer.
  • Utilizing a one-route all-dry etching process (ORADEP) for reproducible and uniform device fabrication.
  • Characterization of the five-story VIUM device in independent DRAM and flash memory modes, as well as a unified mode.

Main Results:

  • The five-story VIUM device exhibited significantly enhanced sensing current drivability compared to one-story unified memory (UM).
  • The VIUM demonstrated superior switching endurance and a larger sensing memory window in unified mode operation.
  • The device showed reliable reproducibility, stiction-free stability, and high uniformity.

Conclusions:

  • The vertically integrated nanowire-based device successfully integrates DRAM and flash memory functionalities into a single transistor.
  • The developed VIUM device offers enhanced performance and endurance, proving its practicality for next-generation SoC architectures.
  • This work highlights the versatility of vertically integrated nanowire configurations for diverse electronic applications.