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FPGA-based rate-adaptive LDPC-coded modulation for the next generation of optical communication systems
Optics Express
|September 9, 2016
Summary
This study introduces a rate-adaptive Forward Error Correction (FEC) scheme using Low-Density Parity-Check (LDPC) codes and a reconfigurable FPGA architecture. The system achieves significant coding gains for various modulations, enhancing data transmission reliability.
Area of Science:
- Digital Communications
- Error Correction Coding
- Field-Programmable Gate Arrays (FPGA)
Background:
- Traditional Forward Error Correction (FEC) schemes often lack adaptability to varying channel conditions.
- Low-Density Parity-Check (LDPC) codes offer powerful error correction capabilities but require efficient implementation for real-time applications.
- Software reconfigurable architectures are crucial for flexible and future-proof digital communication systems.
Purpose of the Study:
- To propose a novel rate-adaptive FEC scheme utilizing LDPC codes.
- To design and emulate a unified software reconfigurable FPGA architecture for the proposed scheme.
- To evaluate the performance of the rate-adaptive LDPC codes across different modulation schemes and error protection strategies.
Main Methods:
- Development of a rate-adaptive LDPC code construction based on shortening.
- Implementation and emulation of a unified, software reconfigurable FPGA architecture.
- Performance evaluation using FPGA emulation for Binary Phase Shift Keying (BPSK) and higher-order modulations (QPSK, 8-QAM, 16-QAM, 32-QAM, 64-QAM).
- Application of unequal error protection by assigning different LDPC codes to different bit positions.
Main Results:
- The proposed rate-adaptive LDPC codes achieved coding gains from 13.08 dB to 14.28 dB at a post-FEC Bit Error Rate (BER) of 10-15 for BPSK.
- The scheme demonstrated effectiveness with higher-order modulations (QPSK to 64-QAM) across a broad range of signal-to-noise ratios.
- Unequal error protection yielded an additional 0.5 dB gain for 16-QAM and 64-QAM compared to conventional LDPC coded modulation.
Conclusions:
- The proposed rate-adaptive LDPC coding scheme combined with a unified FPGA architecture offers significant performance improvements and flexibility.
- The system effectively supports a wide range of modulation formats and channel conditions.
- Unequal error protection provides a valuable method for further enhancing system performance in specific applications.
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