A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor

Area of Science:

• Electrical Engineering
• Image Sensor Technology
• Low-Power Design

Background:

• Digital CMOS Time Delay Integration (TDI) image sensors are crucial for high-speed imaging.
• Reducing power consumption in these sensors is a significant challenge without compromising performance.
• Existing quantization methods can be power-intensive.

Purpose of the Study:

• To propose an accumulation technique for digital CMOS TDI image sensors to reduce power consumption.
• To maintain or improve imaging rate while decreasing energy usage.
• To address power demands associated with quantization in TDI sensors.

Main Methods:

• Developed a novel accumulation technique involving pixel array division for coarse and fine quantization.
• Implemented a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC) based TDI sensor chain.
• Designed two versions of a 16-stage digital domain CMOS TDI image sensor chain in a 0.18 µm CMOS process: one with and one without the proposed technique.

Main Results:

• The proposed technique reduced average power consumption from 7.4 × 10⁻⁸ J/line to 6.47 × 10⁻⁸ J/line.
• Achieved a linearity of 99.99% with the new technique, compared to 99.74% without it.
• The technique effectively reduces the total required bit numbers for quantization.

Conclusions:

• The proposed accumulation technique offers a viable solution for reducing power consumption in digital CMOS TDI image sensors.
• This method successfully lowers energy usage without degrading imaging rates or linearity.
• The technique demonstrates significant power savings and improved linearity, making it suitable for advanced imaging applications.