Two Dimensional Electrostrictive Field Effect Transistor (2D-EFET): A sub-60mV/decade Steep Slope Device with High ON...

Area of Science:

• Materials Science
• Solid State Physics
• Nanotechnology

Background:

• Current Field-Effect Transistors (FETs) face limitations in power consumption and performance scaling.
• Aggressive channel length scaling in traditional FETs leads to increased leakage currents and power demands.
• Post-Complementary Metal-Oxide-Semiconductor (CMOS) computing requires novel device architectures for enhanced efficiency.

Purpose of the Study:

• To propose a disruptive device concept, the two-dimensional electrostrictive field effect transistor (2D-EFET).
• To achieve low power consumption and high performance simultaneously for next-generation computing.
• To enable aggressive channel length scaling beyond current technology nodes.

Main Methods:

• Utilizing voltage-induced strain transduction via an electrostrictive gate oxide.
• Applying gate bias to induce expansion in the electrostrictive material, creating out-of-plane stress on a 2D channel.
• Dynamically reducing the bandgap of the 2D channel material by decreasing inter-layer distance.

Main Results:

• The 2D-EFET demonstrates a subthreshold swing below 60mV/decade, outperforming existing FETs.
• Achieved considerably higher ON current compared to state-of-the-art FETs.
• The device architecture supports scaling beyond the 10nm technology node due to its ultra-thin body and electrostatic integrity.

Conclusions:

• The 2D-EFET operates by modulating the bandgap of the 2D channel material through strain transduction.
• Internal voltage amplification leads to the superior subthreshold swing.
• This device offers a promising pathway for low-power, high-performance post-CMOS computing with enhanced scalability.