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Field Effect Transistor01:29

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Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
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Updated: Mar 13, 2026

Development and Functionalization of Electrolyte-Gated Graphene Field-Effect Transistor for Biomarker Detection
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Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications.

Seul Ki Hong1, Jae Hoon Bong1, Byung Jin Cho1

  • 1Department of Electrical Engineering, KAIST, Daejeon, 305-701, Korea.

Small (Weinheim an Der Bergstrasse, Germany)
|October 27, 2016
PubMed
Summary

A novel vertically formed graphene stripe (GS) is presented for 3D electronics. This method avoids complex transfer and etching, enabling scalable 3D graphene nanoribbon field-effect transistor (FET) applications.

Keywords:
3D devicesatomic layer depositionfield-effect transistorsgraphene stripegraphene transfer

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Area of Science:

  • Materials Science
  • Nanotechnology
  • Electrical Engineering

Background:

  • Graphene nanoribbons (GNRs) are promising for advanced electronics.
  • Conventional GNR fabrication involves complex transfer and etching processes.
  • 3D integration of electronic components is a key challenge in modern technology.

Purpose of the Study:

  • To demonstrate a new method for fabricating vertically aligned graphene stripes (GS).
  • To explore the potential of vertically formed GS for 3D electronic applications.
  • To assess the scalability and process integration of the proposed GS fabrication.

Main Methods:

  • Fabrication of a 100-nm wide vertically formed graphene stripe along a nickel film sidewall.
  • Engineering the nickel film thickness using atomic layer deposition (ALD) to control GS width.
  • Integration of the GS into field-effect transistors (FETs).

Main Results:

  • Successfully demonstrated a 100-nm wide vertically formed graphene stripe.
  • Showcased the ability to scale down GS width by controlling ALD Ni film thickness.
  • Developed a fabrication process compatible with commercial vertical NAND flash memory manufacturing.

Conclusions:

  • The vertically formed GS offers a simplified fabrication route compared to conventional GNRs.
  • The process is highly scalable and integrates well with existing semiconductor manufacturing techniques.
  • This approach holds significant potential for next-generation 3D advanced FET applications.