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Symmetric Level Index Arithmetic in Simulation and Modeling.

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The MasPar MP-1 As a Computer Arithmetic Laboratory.

Michael A Anuta1, Daniel W Lozier2, Peter R Turner3

  • 1Cray Research Inc., Calverton, MD 20705.

Journal of Research of the National Institute of Standards and Technology
|January 1, 1996
PubMed
Summary
This summary is machine-generated.

This study explores using a massively parallel SIMD computer architecture for simulating computer arithmetic. The DEC/MasPar MP-1 enables flexible simulations, allowing examination of speed-area tradeoffs for arithmetic systems.

Keywords:
computer arithmeticfixed-point and floating-point arithmeticlogarithmic and level-index arithmeticresidue number system arithmeticserial and parallel simulation of computer arithmetic

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Area of Science:

  • Computer Science
  • Computational Mathematics
  • Parallel Computing

Background:

  • Massively parallel computer architectures offer unique advantages for simulating complex computational processes.
  • The simplicity of individual processors in SIMD (Single Instruction, Multiple Data) systems facilitates efficient arithmetic simulations.
  • Previous simulations often lacked the flexibility to explore diverse arithmetic implementations and performance trade-offs.

Purpose of the Study:

  • To present a blueprint for utilizing a DEC/MasPar MP-1 massively parallel SIMD architecture for computer arithmetic simulations.
  • To demonstrate the architecture's suitability for simulating various arithmetic systems, including level-index (LI) and symmetric level-index (SLI).
  • To investigate the potential for speed-area trade-offs through different simulation strategies.

Main Methods:

  • Utilizing a DEC/MasPar MP-1 with 4096 processors arranged in a square array.
  • Implementing arithmetic operations by distributing them across the processor array or executing them on individual processors.
  • Simulating specific arithmetic systems, with a detailed focus on level-index and symmetric level-index implementations.

Main Results:

  • The SIMD architecture effectively supports the simulation of diverse computer arithmetic forms.
  • Distributing operations across the array allows simulation of hardware chips, while individual processor execution simulates parallel implementations.
  • The system facilitates the examination of speed-area trade-offs in arithmetic simulations.

Conclusions:

  • The DEC/MasPar MP-1 architecture is a powerful tool for simulating computer arithmetic, offering flexibility and performance insights.
  • The described simulation approach enables detailed analysis of arithmetic systems like LI and SLI.
  • This work provides a foundation for further research in parallel computer arithmetic and its efficient implementation.