Demonstration of Complementary Ternary Graphene Field-Effect Transistors

Area of Science:

• Materials Science
• Electronics Engineering
• Computer Science

Background:

• Semiconductor devices face increasing demand for power reduction.
• Ternary logic offers higher information density and lower device density compared to binary logic.
• A single device for ternary logic has remained elusive for decades.

Purpose of the Study:

• To demonstrate a novel device for ternary logic.
• To achieve a functional ternary logic device at room temperature.
• To pave the way for extreme-low-power computing.

Main Methods:

• Fabrication of a ternary graphene field-effect transistor (TGFET).
• Introduction of a metal strip in the graphene channel to create N-P-N or P-N-P doping patterns.
• Modulation of the metal's work function to achieve ternary function and room-temperature operation.

Main Results:

• Demonstration of a single TGFET exhibiting three discrete current states.
• Successful implementation of a standard ternary inverter operating at room temperature.
• Validation of the feasibility for general ternary logic architecture using complementary TGFETs.

Conclusions:

• The demonstrated TGFET is a key stepping-stone for extreme-low-power computing.
• This work overcomes previous limitations in achieving a single device for ternary logic.
• The findings open new avenues for next-generation electronic devices and architectures.