Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors

Area of Science:

• Semiconductor Device Physics
• Nanotechnology
• Materials Science

Background:

• Conventional tunneling field-effect transistors (TFETs) face challenges in achieving optimal performance for low-power applications.
• Improving the surface-to-volume ratio in TFETs is crucial for enhancing carrier tunneling and device efficiency.

Purpose of the Study:

• To propose and investigate novel three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs).
• To evaluate the performance enhancements of CS TFETs compared to conventional TFETs, focusing on subthreshold swing and on-state current.

Main Methods:

• Fabrication of CS silicon vertical nanowire TFETs using conventional CMOS technology.
• Analysis of device characteristics, including subthreshold swing (SS), on-state current, and off-state current.
• Parametric study involving nanowire height, equivalent oxide thickness (EOT), and nanowire array configuration.

Main Results:

• CS TFETs exhibit a significantly lower subthreshold swing (SS) and higher on-state current due to their high surface-to-volume ratio.
• On-state current is tunable by adjusting nanowire height, EOT, and array density.
• Off-state current can be managed via selective epitaxial growth for power savings.
• Optimized CS TFETs (0.8 nm EOT, aspect ratio 20) achieve SS below 60 mV/dec and superior on/off ratios at various voltages.

Conclusions:

• Core-shell silicon vertical nanowire TFETs offer a promising pathway for next-generation low-power electronic devices.
• The proposed TFET architecture provides enhanced performance with potential for low fabrication cost and high device density.
• These devices are suitable for applications demanding high efficiency and minimal power consumption.