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Area of Science:

  • Materials Science
  • Electrical Engineering
  • Computer Engineering

Background:

  • Resistive Random-Access Memory (RRAM) faces challenges with sneak paths limiting array scalability.
  • Existing RRAM arrays often require selector devices to mitigate sneak path issues, adding complexity and cost.

Purpose of the Study:

  • To realize a record-large 128x128 One-Resistor (1R) RRAM array.
  • To demonstrate effective sneak path mitigation without selector devices.
  • To achieve extremely low read currents in a large RRAM array.

Main Methods:

  • Fabrication of a 128x128 RRAM array using a novel One-Resistor (1R) architecture.
  • Implementation of a circuit design featuring a reference point using a half-selected cell.
  • Integration of a differential amplifier (DA) for improved read performance.

Main Results:

  • Successfully realized a 128x128 1R RRAM array, a record size.
  • Achieved a significant Low-Resistive State (LRS)/High-Resistive State (HRS) current difference (378 nA/16 nA) even in worst-case cells, without selectors.
  • Attained extremely low read current of 9.7 μA through device and circuit co-design.

Conclusions:

  • The developed 1R RRAM array architecture effectively overcomes sneak path limitations for large-scale integration.
  • The novel circuit design with a reference point and DA enables high performance and low read currents.
  • This work presents a significant step towards practical, high-density RRAM non-volatile memory.