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DeepX: Deep Learning Accelerator for Restricted Boltzmann Machine Artificial Neural Networks.

Lok-Won Kim

    IEEE Transactions on Neural Networks and Learning Systems
    |March 14, 2017
    PubMed
    Summary
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    This study introduces a novel hardware accelerator for artificial neural networks (ANNs), specifically Restricted Boltzmann Machines (RBMs). The FPGA-based design significantly boosts computational performance for deep learning tasks.

    Area of Science:

    • Computer Engineering
    • Artificial Intelligence
    • Hardware Acceleration

    Background:

    • General-purpose processors struggle with the computational demands of modern deep learning applications.
    • Custom hardware architectures are necessary for accelerating computationally intensive tasks like artificial neural networks (ANNs).
    • Restricted Boltzmann Machines (RBMs) are a type of ANN with significant computational requirements.

    Purpose of the Study:

    • To propose and implement a fully pipelined hardware acceleration architecture for RBM ANNs.
    • To address the high computational demand limiting practical applications of deep learning.
    • To enhance the performance of RBM ANNs beyond existing software and hardware solutions.

    Main Methods:

    • Designed and implemented a fully pipelined RBM ANN accelerator.

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    Deep Neural Networks for Image-Based Dietary Assessment
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  • Integrated the accelerator into a state-of-the-art Field-Programmable Gate Array (FPGA) device (Xilinx Virtex 7 XC7V-2000T).
  • Evaluated performance using a network size with 128 input cases per batch at a 303-MHz clock frequency.
  • Main Results:

    • Achieved a computational performance of 301 billion connection-updates-per-second.
    • Demonstrated approximately 193 times higher performance compared to a software solution on general-purpose processors.
    • Outperformed a previous FPGA implementation by over 4 times (12 times in batch learning).

    Conclusions:

    • The proposed pipelined RBM ANN accelerator significantly alleviates computational demands.
    • FPGA-based hardware acceleration offers substantial performance gains for deep learning.
    • This architecture provides a viable solution for accelerating complex ANNs in resource-intensive applications.