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Related Experiment Videos

ASIC chipset design to generate block-based complex holographic video.

Young-Ho Seo, Yoon-Hyuk Lee, Dong-Wook Kim

    Applied Optics
    |April 5, 2017
    PubMed
    Summary

    This study introduces a novel hardware architecture for real-time hologram generation using application-specific integrated circuit technology. The design enables parallel block-based calculations for efficient and stable hologram production.

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    Area of Science:

    • Computer Engineering
    • Optics and Photonics
    • Integrated Circuit Design

    Background:

    • Hologram generation traditionally involves complex computations.
    • Real-time holographic display requires efficient hardware solutions.

    Purpose of the Study:

    • To propose a novel hardware architecture for efficient hologram generation.
    • To enable real-time holographic display using application-specific integrated circuits (ASICs).

    Main Methods:

    • Developed a very large-scale integrated circuit (VLSI) architecture using ASIC technology.
    • Implemented block-based calculations for parallel hologram segment generation.
    • Optimized memory access for various hologram sizes.

    Main Results:

    Related Experiment Videos

    • The hardware architecture was fabricated using Hynix 0.18 μm CMOS technology.
    • The chip features approximately 448K gate counts and a silicon size of 3.592mm x 3.592mm.
    • Achieved stable operation at a 200 MHz clock frequency for complex hologram generation.

    Conclusions:

    • The proposed hardware architecture enables efficient, real-time hologram generation.
    • The parallel block-based approach optimizes computational performance and memory usage.
    • The implemented ASIC demonstrates the feasibility of high-performance holographic systems.