A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix
Min Zhang1, Hai Wang2, Yan Liu3
1School of Electro-Mechanical Engineering, Xidian University, Xi'an 710071, China. minzhanghk@gmail.com.
Sensors (Basel, Switzerland)
|April 20, 2017
Summary
A new field programmable gate array (FPGA) based time-to-digital converter (TDC) offers high resolution and stability. This novel FPGA TDC design achieves 7.4 ps resolution, with low integral and differential nonlinearity.
Area of Science:
- Digital electronics
- Integrated circuit design
- Signal processing
Background:
- Time-to-digital converters (TDCs) are crucial for precise timing measurements.
- Existing TDC designs often face challenges with temperature and voltage sensitivity.
- Field programmable gate arrays (FPGAs) offer a flexible platform for custom hardware development.
Purpose of the Study:
- To propose and test a high-resolution TDC implemented on an FPGA.
- To introduce a novel TDC architecture utilizing routing resources for delay elements.
- To evaluate the performance and stability of the proposed FPGA-based TDC.
Main Methods:
- Implementation of a new TDC architecture featuring a 1024-unit measurement matrix.
- Utilization of FPGA routing resources as delay elements for enhanced stability.
- Experimental testing to determine measurement resolution, integral nonlinearity (INL), and differential nonlinearity (DNL).
Main Results:
- Achieved a measurement resolution of 7.4 ps.
- Recorded Integral Nonlinearity (INL) of 11.6 ps and Differential Nonlinearity (DNL) of 5.5 ps.
- Demonstrated insensitivity to temperature and voltage variations due to the novel design.
Conclusions:
- The proposed FPGA-based TDC offers high performance with excellent resolution and linearity.
- The design leverages FPGA routing resources for improved stability and reduced sensitivity to environmental factors.
- FPGA implementation provides advantages in terms of ease of implementation, cost-effectiveness, and reduced development time.
