Study of the pedestal process for reducing sidewall scattering in photonic waveguides

In this work we investigate the principles of an alternative method for defining sidewall in optical waveguides fabricated using planar technology. The efficiency of this method is demonstrated through simulations and experimental results regarding propagation losses of a solid core ARROW waveguide fabricated on silicon substrate. It is well known that waveguides fabricated using sidewalls etched via Reactive Ion Etching (RIE) can present high sidewall roughness, especially if metallic hard-masks are used. This is largely responsible for the undesirable losses observed in these waveguides. The basic strategy of the proposed method is to do the etching step, in the fabrication of the waveguides, before the deposition of the core, so as to have the lower cladding layer and part of the silicon substrate etched away. Only after this, is the core of the waveguide deposited. This results in a waveguide sustained by a silicon pedestal. With this process, losses as low as 0.45 dB cm^-1 for multimode and 0.84 dB cm^-1 for single mode waveguides are obtained. The numerical simulations demonstrate that roughness in sidewalls implicates in propagation losses which are at least five times larger that those in the bulk of the material, thus corroborating the idea behind the proposed method.