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Related Experiment Video

Updated: Mar 1, 2026

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A Hardware-Efficient Scalable Spike Sorting Neural Signal Processor Module for Implantable High-Channel-Count Brain

Yuning Yang, Sam Boling, Andrew J Mason

    IEEE Transactions on Biomedical Circuits and Systems
    |May 26, 2017
    PubMed
    Summary
    This summary is machine-generated.

    A new hardware-efficient neural signal processor (NSP) enables high-channel-count brain machine interfaces. This scalable design addresses data bandwidth limitations for fully implantable wireless neural recording systems.

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    Area of Science:

    • Neuroscience
    • Biomedical Engineering
    • Electrical Engineering

    Background:

    • Next-generation brain-machine interfaces require high-channel-count neural recording systems.
    • Wireless, fully implantable systems face data bandwidth bottlenecks.

    Purpose of the Study:

    • To develop a hardware-efficient neural signal processor (NSP) for high-channel-count neural recording.
    • To design a scalable multichannel spike sorting NSP module for implantable wireless systems.

    Main Methods:

    • Designed a multichannel spike sorting NSP module with integrated spike detector, feature extractor, and classifier blocks.
    • Optimized block utilization for parallel processing, considering power, area, and speed.
    • Developed a prototype 32-channel NSP module tested on FPGA with synthesized datasets.

    Main Results:

    • Achieved 0.75 μW power and 0.023 mm² area per channel in 130 nm CMOS.
    • Demonstrated scalability for up to 690 channels on a 4x4 mm² electrode array.
    • Validated performance across a wide range of signal-to-noise ratios.

    Conclusions:

    • The developed NSP module is highly hardware-efficient and scalable.
    • This design effectively addresses bandwidth limitations for implantable neural recording.
    • Enables future high-density neural monitoring for advanced brain-machine interfaces.