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A high-resolution programmable Vernier delay generator based on carry chains in FPGA.

Ke Cui1, Xiangyu Li2, Rihong Zhu1

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This study introduces a high-resolution delay generator on a single FPGA chip using carry chains. This efficient design offers a large dynamic range and high precision for physical instruments.

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Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Instrumentation

Background:

  • Accurate timing is crucial for many physical instruments.
  • Existing delay generators may lack sufficient resolution or dynamic range.
  • Field-Programmable Gate Arrays (FPGAs) offer a flexible platform for custom hardware development.

Purpose of the Study:

  • To present a novel architecture for a high-resolution delay generator.
  • To implement this generator on a single FPGA chip.
  • To achieve both a large dynamic range and high resolution.

Main Methods:

  • Utilizing dedicated carry chains within an FPGA.
  • Organizing carry chains in a Vernier delay loop style.
  • Implementing a coarse and fine delay step architecture.

Main Results:

  • Achieved a resolution of 38.6 ps.
  • Exhibited low differential nonlinearity ([-0.18 LSB, 0.24 LSB]) and integral nonlinearity ([-0.02 LSB, 0.01 LSB]).
  • Demonstrated resource efficiency using 668 look-up tables and 146 registers.

Conclusions:

  • The proposed FPGA-based delay generator meets high-resolution and linearity requirements.
  • The Vernier delay loop architecture effectively provides fine delay steps.
  • This design offers an efficient and precise solution for timing applications in physical instruments.