A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Device Fabrication

Background:

• Parasitic capacitance and the number of photo-masks increase fabrication costs and limit operational speed in thin-film transistors (TFTs).
• Traditional TFT fabrication processes can damage source/drain electrodes during etching and require multiple photo-masks.

Purpose of the Study:

• To propose a new, cost-effective, and high-speed fabrication process for thin-film transistors (TFTs).
• To reduce the number of photo-masks and minimize parasitic capacitance in TFTs.

Main Methods:

• A novel two-photo-mask fabrication process utilizing backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes.
• Development of a self-aligned structure without an etching-stop layer.
• Fabrication of thin-film transistors (TFTs) and inverter circuits using the proposed method.

Main Results:

• The proposed process achieved comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade) to traditional methods.
• Significantly decreased delay time in inverters fabricated with the new process.
• Reduced parasitic capacitance and fewer photo-masks required compared to conventional processes.

Conclusions:

• The proposed two-photo-mask process offers a viable alternative for fabricating high-performance thin-film transistors (TFTs).
• This method effectively reduces fabrication costs and enhances operational speed by minimizing parasitic capacitance and photo-mask count.
• The BUV and BLO integration provides a damage-free etching solution for source/drain electrodes.