Hardware emulation of stochastic p-bits for invertible logic

Area of Science:

• Nanoelectronics
• Computational Science
• Materials Science

Background:

• Traditional logic devices rely on stable states for binary representation.
• A novel paradigm utilizes three-terminal stochastic units, or p-bits, exhibiting tunable, fluctuating outputs between 0 and 1.
• These p-bits can form networks, enabling optimization, inference, and unique invertible Boolean logic operations.

Purpose of the Study:

• To investigate the hardware implementation feasibility of p-bit-based invertible logic.
• To demonstrate the practical application of p-bits in computational tasks beyond simulations.
• To establish a foundation for future nano-device implementations of stochastic computing.

Main Methods:

• Emulation of p-bits using individual microcontrollers.
• Construction of a 4-bit ripple carry adder utilizing 48 emulated p-bits.
• Implementation of a 4-bit multiplier using 46 emulated p-bits, functioning as a factorizer.

Main Results:

• Successful emulation and operation of a 4-bit ripple carry adder using p-bits.
• Demonstration of a 4-bit multiplier functioning as a factorizer through p-bit implementation.
• Validation of invertible logic principles in a hardware-emulated setting.

Conclusions:

• Hardware emulation confirms the potential of p-bits for implementing complex logic functions.
• The results represent a significant stride towards realizing stochastic computing with nanoelectronic devices.
• P-bit networks offer a promising alternative for future low-power, high-performance computing architectures.