Mitigating the influence of wafer topography on the implantation process in optical lithography

Residual resist in the gate caused by wafer topography would prevent part of the fins from ion implantation. It is a big concern in semiconductor manufacturing. The optical interference intensity improvement of the region located between two gates induced by substituting the material of the sidewall of the gate with silicon oxide is discussed in this Letter. The relationship between the thickness of silicon oxide and optical intensity at the fin's top is also established from the rigorous coupled wave analysis method. Based on this correlation, the method for mitigating the wafer topography of the implantation process is put forward and evaluated from rigorous numerical simulations. The proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost saver in mass production.