Imaging Atomic Scale Dynamics on III-V Nanowire Surfaces During Electrical Operation.

Area of Science:

• Materials Science
• Surface Science
• Nanotechnology

Background:

• Semiconductor device functionality is increasingly limited by atomic-scale surface and interface properties.
• These properties can dynamically change under applied voltages, impacting device performance and reliability.
• Current methods lack the ability to observe these changes in situ at atomic resolution across the entire device.

Purpose of the Study:

• To develop and demonstrate a novel device platform enabling simultaneous scanning tunneling microscopy (STM) imaging and full electrical operation.
• To investigate the atomic-scale surface behavior of semiconductor nanowires under applied bias.
• To explore the potential for new electronic functionalities arising from bias-induced surface restructuring.

Main Methods:

• Development of a versatile device platform compatible with standard fabrication and scanning instrumentation.
• Integration of STM imaging capabilities with full electrical operation across the device.
• Proof-of-principle measurements on Indium Arsenide (InAs) and Gallium Arsenide (GaAs) nanowire devices with applied biases up to 4V.

Main Results:

• Demonstration of STM imaging with atomic-scale resolution across the entire device during electrical operation.
• Observation of unexpected atomic defect removal and surface smoothing on InAs nanowires under applied bias.
• Contradiction of the anticipated increase in defects and electromigration-related failures.

Conclusions:

• The developed platform enables in-situ atomic-scale investigation of device surfaces during operation.
• Applied bias can induce beneficial surface restructuring, leading to defect removal and morphological smoothing.
• This approach opens avenues for fundamental studies of device reliability and the discovery of novel electronic functionalities.