An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Multichannel neural recording systems require high Common Mode Rejection Ratio (CMRR) for accurate signal acquisition.
• Conventional Driven Right Leg (DRL) circuits often occupy significant chip area, limiting miniaturization.
• Analog Front Ends (AFEs) are crucial components in amplifying and digitizing biological signals.

Purpose of the Study:

• To develop an integrated multichannel neural recording AFE with a novel, area-efficient DRL circuit.
• To enhance the CMRR performance of the AFE system.
• To provide a compact and power-efficient solution for biomedical recording.

Main Methods:

• Design of an AC-coupled, low-noise programmable-gain amplifier.
• Implementation of a capacitor-less, area-efficient DRL block.
• Integration with a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).
• Fabrication in a 0.18-μm CMOS process.

Main Results:

• Achieved a 90% chip area reduction compared to conventional DRL circuits.
• Demonstrated enhanced CMRR performance of 110 dB.
• AFE provides 54dB/60dB gain settings with low power consumption (1 μA/channel) at 1 V supply.
• Input-referred noise is 4 μVrms from 1 Hz to 10 kHz.

Conclusions:

• The proposed capacitor-less DRL design offers significant area savings and improved CMRR.
• The integrated AFE is well-suited for multichannel biomedical recording applications.
• The design achieves excellent noise and power efficiency.