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Related Concept Videos

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

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In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
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Generation and Coherent Control of Pulsed Quantum Frequency Combs
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Photonic integrated circuit implementation of a sub-GHz-selectivity frequency comb filter for optical clock

Zihan Geng, Yiwei Xie, Leimeng Zhuang

    Optics Express
    |November 3, 2017
    PubMed
    Summary

    We developed a compact photonic integrated circuit for optical clock multiplication using a novel ring-resonator-assisted interferometer. This device functions as a reconfigurable optical frequency comb filter, enabling high-speed signal processing.

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    Area of Science:

    • Photonics
    • Integrated Optics
    • Optical Signal Processing

    Background:

    • Optical clock multipliers and frequency comb filters are crucial for high-speed optical communication and signal processing.
    • Existing solutions often face challenges with complexity, size, and reconfigurability.

    Purpose of the Study:

    • To demonstrate a novel photonic integrated circuit for optical clock multiplication.
    • To implement a reconfigurable optical frequency comb filter with high selectivity and low complexity.

    Main Methods:

    • Design and fabrication of a ring-resonator-assisted asymmetrical Mach-Zehnder interferometer in a Sagnac loop.
    • Utilizing a high-index-contrast stoichiometric silicon nitride (Si3N4/SiO2) waveguide platform.
    • Experimental characterization of the filter's passband and demonstration of repetition rate multiplication.

    Main Results:

    • Achieved a sub-GHz selectivity with a -3-dB bandwidth of 0.6 GHz and a -20-dB bandwidth of 1.2 GHz.
    • Demonstrated five-fold repetition rate multiplication of optical clock signals (e.g., 2.5 Gpulses/s to 12.5 Gpulses/s).
    • The device exhibits low loss, small size, and large bandwidth.

    Conclusions:

    • The developed photonic integrated circuit offers a device-compact solution for optical clock multipliers and frequency comb filters.
    • This technology has potential applications in RF spectrum scanners, photonic radars, WDM switches, and LIDARs.
    • The novel circuit topology enables efficient comb spectrum processing on an integrated platform.