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All-electronic Nanosecond-resolved Scanning Tunneling Microscopy: Facilitating the Investigation of Single Dopant Charge Dynamics
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Random dopant fluctuations and statistical variability in n-channel junctionless FETs.

N D Akhavan1, G A Umana-Membreno1, R Gu1

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Random dopant fluctuations impact silicon junctionless nanowire transistor (JNT) electrical variability. Optimizing doping density in JNTs achieves near-ideal performance, enabling continued scaling in silicon CMOS technology.

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Area of Science:

  • Semiconductor device physics
  • Quantum transport simulations
  • Advanced materials science

Background:

  • Random dopant fluctuations (RDF) significantly impact nanoscale transistor variability.
  • Silicon junctionless nanowire transistors (JNTs) are promising for future integrated circuits.
  • Understanding RDF effects is crucial for reliable device performance and scaling.

Purpose of the Study:

  • To investigate the influence of random dopant fluctuations on the statistical variability of n-channel JNT electrical characteristics.
  • To explore the impact of varying doping densities and gate lengths on JNT performance.
  • To identify optimal doping strategies for minimizing variability in JNTs.

Main Methods:

  • Three-dimensional quantum simulations utilizing the non-equilibrium Green's function (NEGF) formalism.
  • Atomistic modeling of JNTs with gate lengths of 5, 10, and 15 nm.
  • Simulation of average doping densities at 2 × 10^19, 6 × 10^19, and 1 × 10^20 cm^-3.

Main Results:

  • Demonstrated a direct correlation between doping density and statistical variability in JNT electrical properties.
  • Showcased that specific doping density adjustments can significantly reduce device-to-device variations.
  • Identified optimal doping ranges for achieving high performance and low variability across different gate lengths.

Conclusions:

  • Proper adjustment of doping density in JNTs is critical for mitigating random dopant fluctuation effects.
  • Achieving near-ideal statistical variability and electrical performance is possible through optimized doping.
  • This research provides a pathway for the continued scaling of silicon CMOS technology by improving JNT reliability.