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Related Experiment Video

Updated: Feb 17, 2026

Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors
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A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel.

Seiji Takahashi1, Yi-Min Huang2, Jhy-Jyi Sze3

  • 1Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu 300, Taiwan. seijit@tsmc.com.

Sensors (Basel, Switzerland)
|December 6, 2017
PubMed
Summary

This study demonstrates advanced submicron pixel performance using stacked CMOS image sensor technology. Results show low dark current and read noise, high full well capacity, and minimal blooming for improved image quality.

Keywords:
dark currentfull well capacityimage sensoroptical crosstalkrandom telegraph noiseread noisestacked CMOS image sensorsubmicron pixel

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Area of Science:

  • Semiconductor device physics
  • Image sensor technology

Background:

  • Submicron pixels are crucial for high-resolution imaging.
  • Stacked CMOS image sensor (CIS) technology offers potential performance enhancements.

Purpose of the Study:

  • To investigate the light and dark performance of submicron pixels.
  • To evaluate the impact of advanced node technology and stacked CIS on pixel performance.

Main Methods:

  • Experimental characterization of submicron pixel performance.
  • Simulation of 0.8 μm pixel performance.

Main Results:

  • Achieved a low dark current of 3.2 e-/s at 60 °C.
  • Demonstrated ultra-low read noise of 0.90 e-·rms.
  • Recorded a high full well capacity (FWC) of 4100 e- with 0.5% blooming in 0.9 μm pixels.

Conclusions:

  • Stacked CIS technology enables superior submicron pixel performance.
  • The demonstrated pixel characteristics are promising for next-generation imaging applications.