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Spiking Neural Classifier with Lumped Dendritic Nonlinearity and Binary Synapses: A Current Mode VLSI Implementation

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This study introduces a neuromorphic spiking neural classifier using binary synapses and dendritic nonlinearity. The hardware implementation achieves high accuracy with fewer resources, even with manufacturing imperfections, demonstrating efficient pattern classification.

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Area of Science:

  • Neuromorphic engineering
  • Artificial intelligence
  • Integrated circuit design

Background:

  • Conventional algorithms require significant synaptic resources for classification.
  • Previous software simulations showed potential for binary synapses and structural plasticity.
  • Analog systems face challenges from manufacturing imperfections.

Purpose of the Study:

  • To present a neuromorphic current mode implementation of a spiking neural classifier.
  • To demonstrate the effectiveness of binary synapses and dendritic nonlinearity in hardware.
  • To evaluate the performance of the chip in real-world conditions and compare it to software and conventional machine learners.

Main Methods:

  • Implemented a spiking neural classifier with lumped square law dendritic nonlinearity in a [Formula: see text]m CMOS chip.
  • Utilized binary synapses and structural plasticity algorithms for training.
  • Employed two opposing cells per class to cancel common-mode inputs.
  • Tested the chip on high-dimensional binary patterns and two UCI datasets.

Main Results:

  • The hardware achieved comparable classification accuracy to software simulations, with only a 0.5% reduction.
  • The neuromorphic classifier used two to five times fewer binary synapses than standard machine learners.
  • The chip demonstrated robustness against manufacturing imperfections (23.5% CV for gains, 14.4% for leaks).
  • Static power dissipation was 19 nW per neuronal cell, with 125 pJ/spike energy consumption.

Conclusions:

  • This work presents the first hardware implementation of a classifier exploiting dendritic properties and binary synapses.
  • The developed neuromorphic system offers a resource-efficient approach to pattern classification.
  • The chip demonstrates comparable performance to conventional methods while significantly reducing synaptic resource requirements.