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Scalable excitatory synaptic circuit design using floating gate based leaky integrators.

Vladimir Kornijcuk^1,2, Hyungkwang Lim¹, Inho Kim¹

¹Center for Electronic Materials, Korea Institute of Science and Technology, Seoul, 02792, Republic of Korea.

Scientific Reports

|December 16, 2017

Summary

This summary is machine-generated.

We developed a power-efficient synaptic circuit for neuromorphic engineering that implements spike timing dependent plasticity (STDP) with randomly spiking neurons. This circuit offers weight-dependent adaptation and competitive learning, crucial for brain-inspired computing.

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Area of Science:

Neuromorphic Engineering
Computational Neuroscience
Integrated Circuit Design

Background:

Spike-timing dependent plasticity (STDP) is a fundamental mechanism for synaptic learning in biological neural systems.
Implementing STDP in artificial neural networks, especially with randomly spiking neurons, presents significant engineering challenges.
Existing neuromorphic circuits often struggle with power efficiency and biological plausibility.

Purpose of the Study:

To propose and validate a scalable synaptic circuit architecture capable of realizing STDP.
To achieve STDP compatibility with randomly spiking neurons in a compact and power-efficient design.
To demonstrate key features of synaptic adaptation and weight regulation.

Main Methods:

Circuit simulations were performed using the BSIM 4.6.0 model to verify the circuit's functionality.
The proposed circuit utilizes floating-gate integrators for compact implementation of biologically relevant timescales.
Charge tunneling through area-independent barrier properties governs the relaxation dynamics, enhancing robustness.

Main Results:

The circuit successfully implements weight-dependent STDP, which inherently limits synaptic weight growth.
Competitive synaptic adaptation was demonstrated in both unsupervised and supervised learning scenarios with randomly spiking neurons.
The estimated power consumption is exceptionally low at 34 pW, highlighting significant power efficiency.

Conclusions:

The developed synaptic circuit offers a scalable and power-efficient solution for implementing STDP in neuromorphic systems.
The use of floating-gate integrators and charge tunneling provides a robust and compact design for biologically plausible synaptic dynamics.
The circuit's ability to support weight-dependent adaptation and competitive learning with randomly spiking neurons makes it a promising candidate for advanced neuromorphic applications.