A 64-Channel Versatile Neural Recording SoC With Activity-Dependent Data Throughput.

Area of Science:

• Neurotechnology
• Integrated Circuit Design
• Biomedical Engineering

Background:

• Neural recording integrated circuits face challenges with high data bandwidth, power consumption, and data transmission, especially for wireless applications.
• Exponential scaling of channel counts in microtechnology exacerbates these issues.
• Sparse nature of neural signals offers an opportunity for data reduction.

Purpose of the Study:

• To present a reconfigurable, low-bandwidth, event-driven neural recording system-on-chip (SoC).
• To address power consumption and data transmission challenges in high-channel-count neural recording.
• To enable efficient real-time neural spike detection and data acquisition.

Main Methods:

• Development of a novel 64-channel low-noise, low-power SoC with individually configurable channels.
• Implementation of 10-bit analog-to-digital conversion, digital filtering, and spike detection.
• Utilizing a dual polarity simple threshold for event-driven output of neural spikes and a latency-encoded asynchronous output.

Main Results:

• Achieved a low-noise (2.1 V) and low-power (23 µW/channel) neural recording SoC.
• Demonstrated 2 orders of magnitude data reduction through real-time spike detection.
• Successfully implemented a 64-channel SoC in 0.35-µm CMOS technology, occupying 19.1 mm² silicon area.

Conclusions:

• The developed SoC effectively exploits neural signal sparsity for low-bandwidth, event-driven output.
• The system offers a power-efficient architecture for high-density neural recording, suitable for closed-loop applications.
• Further optimization is possible through advanced technology and voltage scaling for enhanced performance.