VLSI Design of Trusted Virtual Sensors.

Area of Science:

• Integrated Circuit Design
• Embedded Systems Security
• Sensor Technology

Background:

• Virtual sensors offer cost-effective alternatives to physical sensors.
• Ensuring the integrity and security of virtual sensor data is crucial for reliable operation.
• Existing solutions may lack comprehensive security features or efficient hardware implementation.

Purpose of the Study:

• To present a Very Large Scale Integration (VLSI) design of a trusted virtual sensor.
• To achieve a minimum unitary cost with excellent size, speed, and power consumption.
• To ensure the integrity and confidentiality of virtual measurements and the sensor itself.

Main Methods:

• Utilizing a configurable PieceWise-Affine hyper-Rectangular (PWAR) model for virtual sensing.
• Employing an algorithm to optimize PWAR model parameters from input-output data.
• Integrating the AEGIS authenticated encryption algorithm for data integrity and encryption.
• Incorporating a Static Random Access Memory (SRAM) based Physical Unclonable Function (PUF) for sensor integrity.

Main Results:

• A prototype VLSI design in 90-nm CMOS technology with 0.86 mm² silicon area.
• Power consumption of 7.12 mW at 50 MHz during trusted sensing.
• Maximum operating frequency of 85 MHz, enabling response times under 0.25 μs.
• Application to yaw rate estimation in vehicles achieved root mean square errors below 1.1%.

Conclusions:

• The designed trusted virtual sensor offers a secure, efficient, and low-cost solution.
• The SRAM-PUF demonstrates robustness against aging and environmental variations.
• The VLSI implementation meets stringent performance requirements for embedded applications.