On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices.

Area of Science:

• Neuroscience
• Electrical Engineering
• Signal Processing

Background:

• Wireless neural interfaces require efficient data compression due to bandwidth and power limitations.
• Current compressed sensing (CS) encoders use dense matrices, leading to high power and area costs.
• Existing CS methods may offset benefits of reduced data rates with implementation overhead.

Purpose of the Study:

• To propose power and area-efficient compressed sensing (CS) encoder designs for on-chip neural data compression.
• To explore sparse measurement matrices for improved hardware implementation of CS encoders.
• To evaluate the performance and efficiency of novel CS encoder designs.

Main Methods:

• Developed two CS encoder designs utilizing sparse measurement matrices: deterministic quasi-cyclic array code (QCAC) and a-sparse random binary matrix (a-SRBM).
• Proposed efficient Very Large-Scale Integration (VLSI) architectures for both QCAC-CS and a-SRBM encoders.
• Evaluated data recovery performance and hardware implementation costs (area, power).

Main Results:

• Achieved comparable neural data recovery performance with both proposed sparse matrix CS encoders.
• Demonstrated significant reductions in area and total power consumption for the VLSI architectures.
• The sparse matrix approach effectively mitigates the hardware costs of traditional dense CS encoders.

Conclusions:

• Sparse measurement matrices offer a viable and efficient approach for on-chip neural data compression.
• The proposed QCAC-CS and a-SRBM encoders provide a practical solution for power- and area-constrained wireless neural interfaces.
• Efficient VLSI designs enable the deployment of advanced compression techniques in neural recording systems.