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The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Wei Li1, Hongxia Liu2, Shulong Wang3

  • 1Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi'an, 710071, China.

Nanoscale Research Letters
|March 7, 2018
PubMed

Keywords:
DRAMRetention timeSpacer engineeringTunneling FET (TFET)

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