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Related Experiment Video

Updated: Feb 12, 2026

Implementation of a Real-Time Psychosis Risk Detection and Alerting System Based on Electronic Health Records using CogStack
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Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System.

Jian Hua Luo1, Chang Hong Lin1

  • 1Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, #43, Sec. 4, Keelung Rd., Taipei 106, Taiwan. chlin@mail.ntust.edu.tw.

Sensors (Basel, Switzerland)
|April 13, 2018
PubMed
Summary
This summary is machine-generated.

This study introduces an efficient real-time pedestrian detection system on an FPGA, implementing Histogram of Oriented Gradients (HOG) and Support Vector Machine (SVM) algorithms without external memory. The system achieves high frame rates with low FPGA resource utilization.

Keywords:
FPGAHOGSVMhardware accelerationpedestrian detection

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Area of Science:

  • Computer Vision
  • Embedded Systems
  • Digital Hardware Design

Background:

  • Real-time pedestrian detection is crucial for intelligent systems like autonomous vehicles.
  • Existing methods often require significant computational resources or external memory, limiting their applicability in embedded systems.
  • Field-Programmable Gate Arrays (FPGAs) offer a promising platform for efficient hardware acceleration of complex algorithms.

Purpose of the Study:

  • To develop and implement a real-time pedestrian detection system on an FPGA.
  • To integrate both Histogram of Oriented Gradients (HOG) feature extraction and Support Vector Machine (SVM) classification directly onto the FPGA.
  • To achieve low resource utilization and high performance without relying on external memory or processors.

Main Methods:

  • Implementation of the Histogram of Oriented Gradients (HOG) algorithm in hardware on an FPGA.
  • Hardware implementation of a trained Support Vector Machine (SVM) classifier on the same FPGA.
  • Optimization techniques including simplified sub-modules, distributed writing, shift registers, histogram reuse, and block-based SVM window processing.
  • Integration with a digital image sensor for direct input processing.

Main Results:

  • The proposed system successfully implements HOG and SVM algorithms on an FPGA without external memory or processors.
  • Achieved significantly lower FPGA resource utilization compared to prior art implementations.
  • Demonstrated a high frame rate, although with a slight (4.05%) decrease in average detection rate compared to a pure software HOG implementation.
  • The optimizations led to efficient hardware resource usage.

Conclusions:

  • The developed FPGA-based system provides an efficient and resource-conscious solution for real-time pedestrian detection.
  • Hardware acceleration of HOG and SVM on FPGAs is feasible and offers performance advantages for embedded applications.
  • The proposed design demonstrates a viable trade-off between detection accuracy and real-time processing speed for embedded vision systems.