Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System

Area of Science:

• Computer Vision
• Embedded Systems
• Digital Hardware Design

Background:

• Real-time pedestrian detection is crucial for intelligent systems like autonomous vehicles.
• Existing methods often require significant computational resources or external memory, limiting their applicability in embedded systems.
• Field-Programmable Gate Arrays (FPGAs) offer a promising platform for efficient hardware acceleration of complex algorithms.

Purpose of the Study:

• To develop and implement a real-time pedestrian detection system on an FPGA.
• To integrate both Histogram of Oriented Gradients (HOG) feature extraction and Support Vector Machine (SVM) classification directly onto the FPGA.
• To achieve low resource utilization and high performance without relying on external memory or processors.

Main Methods:

• Implementation of the Histogram of Oriented Gradients (HOG) algorithm in hardware on an FPGA.
• Hardware implementation of a trained Support Vector Machine (SVM) classifier on the same FPGA.
• Optimization techniques including simplified sub-modules, distributed writing, shift registers, histogram reuse, and block-based SVM window processing.
• Integration with a digital image sensor for direct input processing.

Main Results:

• The proposed system successfully implements HOG and SVM algorithms on an FPGA without external memory or processors.
• Achieved significantly lower FPGA resource utilization compared to prior art implementations.
• Demonstrated a high frame rate, although with a slight (4.05%) decrease in average detection rate compared to a pure software HOG implementation.
• The optimizations led to efficient hardware resource usage.

Conclusions:

• The developed FPGA-based system provides an efficient and resource-conscious solution for real-time pedestrian detection.
• Hardware acceleration of HOG and SVM on FPGAs is feasible and offers performance advantages for embedded applications.
• The proposed design demonstrates a viable trade-off between detection accuracy and real-time processing speed for embedded vision systems.